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unit IV - Q&A -2 marks -Digital System Design Through VHDL -R19 ECE JNTUA

Digital System Design Through VHDL - Unit II Two Marks Questions and answers

Digital System Design through VHDL  

VHDL Data Types and Data Operators  

Unit II PART A Question and answer  

1 VHDL Data Types and Data Operators  

1. DeÑne Logic Synthesis.  

logic synthesis is a process by which an abstract speciÑcation of desired circuit  

behaviour in register transfer level (RTL) is converted into a logic gates  

2. What is meant by Simulation?  

Simulation refers to modeling of a design, its function and performance. Simulation  

is used for design veriÑcation: Validate assumptions  

3. DiÐerentiate between signal & constant.  

Signals data value can be changed during simulation process while constant data  

value cannot changed. Signals can declared in architecture and entity declaration  

part. Constant can be declared in the process statement.  

4. DeÑne data objects.  

A data object holds a value of a speciÑed type. It is created by means of an object  

declaration. An example is  

variable COUNT: INTEGER;  

This results in the creation of a data object called COUNT which can hold integer  

values. The object COUNT is also declared to be of variable class  

5. DeÑne the purpose of process statement in Behavioral modeling  

A process statement is the primary mechanism used to model the procedural type  

behavior of an entity.Process statements are used to express sequential behavior  

6. What is the diÐerence between signal and variable?  

Signals  

Ò Signal is an object that keeps it past history  

Ò signals are intended to inter process communications  

Ò signal assignment schedules a new value for the signal in the future  

Ò signals are intended to communicate process and subprograms  

Ò Value of the signal must be constant during the entire simulation time  

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Variable  

Ò Variable is an object holds only current value.  

Ò variables are intended keeping intermediate computation steps or results  

Ò A variable assignment immediately replaces the value of the variable  

Ò Variables are used with in the process or subprogram  

Ò value of the variable must be updated immediately.  

7. Write the syntax of loop statement.  

A loop statement is used to iterate through a set of sequential statements. The  

syntax of a loop statement is  

[ loop-label : ] iteration-scheme loop  

sequential-statements  

end loop [ loop-label ] ;  

8. Write the statement for component declaration  

A component instantiated in a structural description must Ñrst be declared using  

a component declaration. A component declaration declares the name and the  

interface of a component. The interface speciÑes the mode and the type of ports.  

The syntax of a simple form of component declaration is  

component component-name  

port ( list-of-interface-ports ) ;  

end component;  

The component-name may or may not refer to the name of an already existing entity  

in a library. If it does not, it must be explicitly bound to an entity; otherwise, the  

model cannot be simulated.  

9. Compare functions and procedures.  

The diÐerence between these is that a VHDL function calculates and returns a  

value. In contrast, a VHDL procedure executes a number of sequential statement  

but don't return a value.  

10. Write the syntax for VHDL function declaration.  

Functions are used to describe frequently used sequential algorithms that return a  

single value. This value is returned to the calling program using a return statement.  

Some of their common uses are as resolution functions, and as type conversion  

functions.  

The general syntax of a subprogram speciÑcation for a function body is function  

function-name (parameter-list) return return-type  

function <name> (<arguments>) return <return type> is  

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{ variable declaration  

begin  

{ Function  

end function <name>  

11. List out operators used in VHDL There are basically Ñve operator groups in  

VHDL. These are  

(a) Arithmetic:  

(b) Relational  

(c) Shift & Rotation  

(d) Logical operators  

(e) Miscellaneous Operator  

12. Write the syntax of libraries in VHDL.  

The library clause makes visible the logical names of design libraries that can be  

referenced within a design unit. The format of a library clause is  

library list-of-logical-library-names; The following example of a library clause  

library TTL, CMOS;  

There are two main forms of the use clause.  

use library-name. primary-unit-name ; {Form 1.  

use library-name. primary-unit-name. Item ; {Form 2.  

13. Write the syntax for VHDL function declaration.JUNE-2018  

The general syntax of a subprogram speciÑcation for a function body is function  

function-name (parameter-list) return return-type  

Functions are used to describe frequently used sequential algorithms that return a  

single value. This value is returned to the calling program using a return statement.  

A function call has the form  

function-name ( list-of-actual-values )  

14. Write the DiÐerent Data types of HDLs.  

ClassiÑcations of Data Type  

(a) PredeÑned Data Type  

(b) User DeÑned Data Type  

PredeÑned Data Type  

(a) BIT : It contains the Binary values 0 and 1. E.g SIGNAL x: BIT;  

x<='1';  

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(b) BIT VECTOR:It contains the set of binary values 0 and 1;  

(c) STD LOGIC - A 8-valued logic system introduced in the IEEE 1164 stan-  

dard.It is the subtype of std ulogic model.  

(d) STD LOGIC VECTOR): It is vector format of std logic data  

(e) STD ULOGIC (STD ULOGIC VECTOR): 9-level logic system  

(f) BOOLEAN: True, False;  

(g) INTEGER: 32-bit integers (from 2,147,483,647 to 2,147,483,647).  

(h) NATURAL: Non-negative integers (from 0 to +2,147,483,647).  

(i) REAL: Real numbers ranging from -1.0E38 to +1.0E38. Not synthesizable.  

(j) Physical literals: Used to inform physical quantities, like time, voltage, etc.  

(k) Character literals: Single ASCII character or a string of such characters. Not  

ynthesizable.  

(l) SIGNED and UNSIGNED: data types dened in the std logic arith package  

15. List out diÐerent types objects used in VHDL  

16. DeÑne deferred constant?  

constant NO OF INPUTS: INTEGER;  

The value of the constant has not been speciÑed in this case. Such a constant  

is called a deferred constant and it can appear only inside a package declaration.  

The complete constant declaration with the associated value must appear in the  

corresponding package body  

17. What is use of Concatenation operators?  

It allows merging two or more arrays. This is done by the & operator.  

The operands for the & (concatenation) operator can be either a one-dimensional  

array type or an element type. The result is always an array type.  

18. DeÑne Generic?  

Generics are a means of passing speciÑc information into an entity. It is often useful  

to pass certain types of information into a design description from its environment.  

Examples of such information are rise and fall delays, and size of interface ports.A  

generic declares a constant object of mode in and can be used in the entity decla-  

ration and its corresponding architecture bodies.  

entity NAND GATE is  

generic (M: INTEGER := 2); { M models the number of inputs.  

port (A: in  

BIT VECTOR(M downto 1); Z: out BIT);  

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end NAND GATE;  

19. List Shift operators used in VHDL  

Ò sll (shift left logical),  

Ò srl (shift right logical),  

Ò sla (shift left arithmetic),  

Ò sra (shift right arithmetic) Ñg ??  

20. What are the Standard data types used in VHDL  

Ò BIT  

Ò BIT VECTOR  

Ò STD LOGIC  

Ò STD LOGIC VECTOR  

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Question Bank- Digital System Design through VHDL - Unit 1

Digital System Design Through VHDL  

Course Code :19A04603  

1

Introduction and Field-Programmable Gate Ar-  

rays  

1. What is a FPGA?  

Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are  

based around a matrix of conÑgurable logic blocks (CLBs) connected via pro-  

grammable interconnects. FPGAs can be reprogrammed to desired application  

or functionality requirements after manufacturing.  

2. What are the characteristics of FPGA?  

Lower complexity, higher speed, volume designs and programmable functions are  

general characteristics.  

1) using FPGA to design ASIC circuit, users can get a suitable chip without chip  

production;  

2) FPGA can be used as the middle sample chip of other full custom or semi custom  

ASIC circuits;  

3) There are abundant Òip Òops and I / O pins in FPGA;  

4) FPGA is used to design ASIC circuit, which has the advantages of short cycle,  

low cost, low risk and stable quality;  

5) FPGA adopts high-speed CHMOS technology with low power consumption; 6)  

FPGA architecture, Òexible logic unit, high integration and wide application range;  

7) FPGA is compatible with the advantages of PLD and general gate array, and  

can realize large-scale circuit.  

3. What is programmable logic array?  

Programmable Logic Array(PLA) is a Ñxed architecture logic device with pro-  

grammable AND gates followed by programmable OR gates.  

PLA is basically a type of programmable logic device used to build a re conÑgurable  

digital circuit.  

Applications:  

PLA is used to provide control over datapath.  

PLA is used as a counter.  

PLA is used as a decoder.  

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PLA is used as a BUS interface in programmed I/O.  

4. Describe the steps in ASIC design Òow?  

Ò Chip SpeciÑcation  

Ò Design Entry / Functional VeriÑcation  

Ò RTL block synthesis / RTL Function  

Ò Chip Partitioning  

Ò Design for Test (DFT) Insertion  

Ò Floor Planning  

Ò Placement  

Ò Clock tree synthesis  

Ò Routing  

Ò Final VeriÑcation (Physical VeriÑcation and Timing)  

Ò GDS II Graphical Data Stream Information Interchange  

5. What are the diÐerent levels of design abstraction at physical design.  

Design application of VHDL to FPGA/ASIC design follows three steps  

Algorithm, register transfer level (RTL), and gate level. Algorithms are unsynthe-  

sizable, RTL is the input to synthesis, gate level is the output from synthesis  

6. What are Programmable Interconnects ?  

It provides the routing path for the programmable logic blocks. Routing paths  

contain wire segments of varying lengths which can be interconnected via electrically  

programmable switches.  

7. What are the languages that are combined together to get VHDL lan-  

guage ? It is a complex and sophisticated language.  

The VHDL language can be regarded as an integrated amalgamation of the follow-  

ing languages: sequential language +  

concurrent language +  

net-list language +  

timing speciÑcations +  

waveform generation language =>VHDL  

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8. What are sequential and concurrent statements? Sequential Statement:  

Whenever one of the signals in the sensitivity list changes, the sequential statements  

are executed in sequence once.  

Wait Statement Concurrent Statement: signal assignment statements inside ar-  

chitecture bodies that are not contained in processes (or body) are called concurrent  

statement  

Simple Assignment statement  

with select statement  

9. List out Applications of FPGA  

Aerospace, automotive, broadcast, consumer electronics, defense, high-performance  

computing, industrial applications, medical applications, and wireless and wired  

communications.  

10. What are advantages of FGPA It is more feasible than discrete design in wiring  

connection. It requires very less space compare to discrete design model. It is  

Òexible design compared to discrete digital design.  

It requires very less design time compared to ASIC design. It is more programming  

Òexible than micro control design.  

It consumes very less power compared to microcontroller based design.  

11. State the features of VHDL.  

Ò Sequential and concurrent activities.  

Ò Design exchange.  

Ò Standardization.  

Ò Documentation.  

Ò Readability.  

Ò Large-scale design.  

Ò A wide range of descriptive capability  

12. Name the abstraction levels.  

Ò Behavioral or system level  

Ò Register Transfer Level (RTL)  

Ò Gate Level  

Ò Layout level or transistor level  

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13. What does hierarchy mean about? Hierarchy means that design has been  

divided in to top level model into lower level model. The top level design has been  

viewed as the system level, then it is subdivided into more sub system and then  

splitted into lower level of design entities.  

14. What are the VHDL structural elements?  

Main units in VHDL:  

Entity  

Architecture  

ConÑguration  

Package  

15. What is entity in VHDL ? A hardware abstraction of this digital system is  

called an entity  

An ENTITY is a list with specications of all input and output pins (PORTS) of  

the circuit.  

Syntax :  

ENTITY entity name IS  

PORT (  

port name : signal mode signal type;  

port name : signal mode signal type;  

...);  

END entity name;  

16. Write a program for nand gate using dataÒow modeling  

library ieee;  

use ieee.std logic 1164.all;  

entity Nand gate is  

port( a, b: in std logic;  

c: out std logic);  

end Nand gate;  

architecture data Òow of Nand gate is  

begin  

c<= a nand b;  

end data Òow;  

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17. Write a progarm of nor gate using Behavioral modeling  

library ieee;  

use ieee.std logic 1164.all;  

entity Nor gate is  

port( a, b: in std logic;  

c: out std logic);  

end Nor gate;  

architecture data Òow of Nor gate is  

begin  

process( a, b)  

begin  

if( a='1' and b='1') then  

c<= '0';  

else  

c<='1'  

end if;  

end data Òow;  

18. Illustrate the Architecture in VHDL.NOV/DEC-2018  

The architecture describes the underlying functionality of the entity and contains  

the statements that model the behavior of the entity. An architecture is always  

related to an entity and describes the behavior of that entity  

The ARCHITECTURE is a description of how the circuit should behave (function).  

Syntax - Architecture Dclaration  

ARCHITECTURE architecture name OF entity name IS  

d- eScilganraaltiDoencslaration, Component declaration etc;  

BEGIN  

(code)  

END architecture name;  

An architecture has two parts: a declarative part (optional), where signals and  

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constants (among others) are declared, and the code part (from BEGIN down).  

19. What is the application of VHDL?  

It is utilized in electronic design automation to express mixed-signal and digital  

systems, such as ICs (integrated circuits) and FPGA (Ñeld-programmable gate ar-  

rays). We can also use VHDL as a general-purpose parallel programming language.  

We utilize VHDL to write text models that describe or express logic circuits.  

20. Illustrate the VHDL program Ñle structure. JUNE-2018  

Objects of Ñle types represent Ñles in the host environment. They provide a mech-  

anism by which a VHDL design communicates with the host environment.  

The syntax of a Ñle type declaration is  

type Ñle-type-name is Ñle of type-name,  

The type-name is the type of values contained in the Ñle. Here are two examples.  

type VECTORS is Ñle of BIT VECTOR;  

type NAMES is Ñle of STRING;  

21. What is structural design element?  

The VHDL structural style describes the interconnection of components within an  

architecture. structural design uses two parts, namely component declaration and  

component instantiations.  

Declare the components in the declarative part of the architecture  

Instance the component in the architecture statement section  

22. What is the diÐerence between signal and variable?  

Signals  

Ò Signal is an object that keeps it past history  

Ò signals are intended to inter process communications  

Ò signal assignment schedules a new value for the signal in the future  

Ò signals are intended to communicate process and subprograms  

Ò Value of the signal must be constant during the entire simulation time  

Variable  

Ò Variable is an object holds only current value.  

Ò variables are intended keeping intermediate computation steps or results  

Ò A variable assignment immediately replaces the value of the variable  

Ò Variables are used with in the process or subprogram  

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Ò value of the variable must be updated immediately.  

23. Write the DiÐerent Data types of HDLs.  

ClassiÑcations of Data Type  

(a) PredeÑned Data Type  

(b) User DeÑned Data Type  

PredeÑned Data Type  

(a) BIT : It contains the Binary values 0 and 1. E.g SIGNAL x: BIT;  

x<='1';  

(b) BIT VECTOR:It contains the set of binary values 0 and 1;  

(c) STD LOGIC - A 8-valued logic system introduced in the IEEE 1164 stan-  

dard.It is the subtype of std ulogic model.  

(d) STD LOGIC VECTOR): It is vector format of std logic data  

(e) STD ULOGIC (STD ULOGIC VECTOR): 9-level logic system  

(f) BOOLEAN: True, False;  

(g) INTEGER: 32-bit integers (from 2,147,483,647 to 2,147,483,647).  

(h) NATURAL: Non-negative integers (from 0 to +2,147,483,647).  

(i) REAL: Real numbers ranging from -1.0E38 to +1.0E38. Not synthesizable.  

(j) Physical literals: Used to inform physical quantities, like time, voltage, etc.  

(k) Character literals: Single ASCII character or a string of such characters. Not  

ynthesizable.  

(l) SIGNED and UNSIGNED: data types dened in the std logic arith package  

24. Write the Entity declaration. Syntax :  

ENTITY entity name IS  

PORT (  

port name : signal mode signal type;  

port name : signal mode signal type;  

...);  

END entity name;  

The mode of the signal can be IN, OUT, INOUT, or BUFFER  

IN and OUT are truly unidirectional pins, while INOUT is bidirectional.BUFFER  

is used when the output signal must be read internally The type of the signal can  

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be BIT, STD LOGIC, INTEGER, etc  

The name of the entity can be basically any name, except VHDL reserved words  

Example - Entity Declartion for nand gate  

ENTITY nand gate IS  

PORT (a, b : IN BIT;  

x:OUT BIT);  

END nand gate;  

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