Digital System Design through VHDL
VHDL Data Types and Data Operators
Unit II PART A Question and answer
1 VHDL Data Types and Data Operators
1. DeÑne Logic Synthesis.
logic synthesis is a process by which an abstract speciÑcation of desired circuit
behaviour in register transfer level (RTL) is converted into a logic gates
2. What is meant by Simulation?
Simulation refers to modeling of a design, its function and performance. Simulation
is used for design veriÑcation: Validate assumptions
3. DiÐerentiate between signal & constant.
Signals data value can be changed during simulation process while constant data
value cannot changed. Signals can declared in architecture and entity declaration
part. Constant can be declared in the process statement.
4. DeÑne data objects.
A data object holds a value of a speciÑed type. It is created by means of an object
declaration. An example is
variable COUNT: INTEGER;
This results in the creation of a data object called COUNT which can hold integer
values. The object COUNT is also declared to be of variable class
5. DeÑne the purpose of process statement in Behavioral modeling
A process statement is the primary mechanism used to model the procedural type
behavior of an entity.Process statements are used to express sequential behavior
6. What is the diÐerence between signal and variable?
Signals
Ò Signal is an object that keeps it past history
Ò signals are intended to inter process communications
Ò signal assignment schedules a new value for the signal in the future
Ò signals are intended to communicate process and subprograms
Ò Value of the signal must be constant during the entire simulation time
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Variable
Ò Variable is an object holds only current value.
Ò variables are intended keeping intermediate computation steps or results
Ò A variable assignment immediately replaces the value of the variable
Ò Variables are used with in the process or subprogram
Ò value of the variable must be updated immediately.
7. Write the syntax of loop statement.
A loop statement is used to iterate through a set of sequential statements. The
syntax of a loop statement is
[ loop-label : ] iteration-scheme loop
sequential-statements
end loop [ loop-label ] ;
8. Write the statement for component declaration
A component instantiated in a structural description must Ñrst be declared using
a component declaration. A component declaration declares the name and the
interface of a component. The interface speciÑes the mode and the type of ports.
The syntax of a simple form of component declaration is
component component-name
port ( list-of-interface-ports ) ;
end component;
The component-name may or may not refer to the name of an already existing entity
in a library. If it does not, it must be explicitly bound to an entity; otherwise, the
model cannot be simulated.
9. Compare functions and procedures.
The diÐerence between these is that a VHDL function calculates and returns a
value. In contrast, a VHDL procedure executes a number of sequential statement
but don't return a value.
10. Write the syntax for VHDL function declaration.
Functions are used to describe frequently used sequential algorithms that return a
single value. This value is returned to the calling program using a return statement.
Some of their common uses are as resolution functions, and as type conversion
functions.
The general syntax of a subprogram speciÑcation for a function body is function
function-name (parameter-list) return return-type
function <name> (<arguments>) return <return type> is
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{ variable declaration
begin
{ Function
end function <name>
11. List out operators used in VHDL There are basically Ñve operator groups in
VHDL. These are
(a) Arithmetic:
(b) Relational
(c) Shift & Rotation
(d) Logical operators
(e) Miscellaneous Operator
12. Write the syntax of libraries in VHDL.
The library clause makes visible the logical names of design libraries that can be
referenced within a design unit. The format of a library clause is
library list-of-logical-library-names; The following example of a library clause
library TTL, CMOS;
There are two main forms of the use clause.
use library-name. primary-unit-name ; {Form 1.
use library-name. primary-unit-name. Item ; {Form 2.
13. Write the syntax for VHDL function declaration.JUNE-2018
The general syntax of a subprogram speciÑcation for a function body is function
function-name (parameter-list) return return-type
Functions are used to describe frequently used sequential algorithms that return a
single value. This value is returned to the calling program using a return statement.
A function call has the form
function-name ( list-of-actual-values )
14. Write the DiÐerent Data types of HDLs.
ClassiÑcations of Data Type
(a) PredeÑned Data Type
(b) User DeÑned Data Type
PredeÑned Data Type
(a) BIT : It contains the Binary values 0 and 1. E.g SIGNAL x: BIT;
x<='1';
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(b) BIT VECTOR:It contains the set of binary values 0 and 1;
(c) STD LOGIC - A 8-valued logic system introduced in the IEEE 1164 stan-
dard.It is the subtype of std ulogic model.
(d) STD LOGIC VECTOR): It is vector format of std logic data
(e) STD ULOGIC (STD ULOGIC VECTOR): 9-level logic system
(f) BOOLEAN: True, False;
(g) INTEGER: 32-bit integers (from 2,147,483,647 to 2,147,483,647).
(h) NATURAL: Non-negative integers (from 0 to +2,147,483,647).
(i) REAL: Real numbers ranging from -1.0E38 to +1.0E38. Not synthesizable.
(j) Physical literals: Used to inform physical quantities, like time, voltage, etc.
(k) Character literals: Single ASCII character or a string of such characters. Not
ynthesizable.
(l) SIGNED and UNSIGNED: data types dened in the std logic arith package
15. List out diÐerent types objects used in VHDL
16. DeÑne deferred constant?
constant NO OF INPUTS: INTEGER;
The value of the constant has not been speciÑed in this case. Such a constant
is called a deferred constant and it can appear only inside a package declaration.
The complete constant declaration with the associated value must appear in the
corresponding package body
17. What is use of Concatenation operators?
It allows merging two or more arrays. This is done by the & operator.
The operands for the & (concatenation) operator can be either a one-dimensional
array type or an element type. The result is always an array type.
18. DeÑne Generic?
Generics are a means of passing speciÑc information into an entity. It is often useful
to pass certain types of information into a design description from its environment.
Examples of such information are rise and fall delays, and size of interface ports.A
generic declares a constant object of mode in and can be used in the entity decla-
ration and its corresponding architecture bodies.
entity NAND GATE is
generic (M: INTEGER := 2); { M models the number of inputs.
port (A: in
BIT VECTOR(M downto 1); Z: out BIT);
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end NAND GATE;
19. List Shift operators used in VHDL
Ò sll (shift left logical),
Ò srl (shift right logical),
Ò sla (shift left arithmetic),
Ò sra (shift right arithmetic) Ñg ??
20. What are the Standard data types used in VHDL
Ò BIT
Ò BIT VECTOR
Ò STD LOGIC
Ò STD LOGIC VECTOR
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