INSTRUCTION
SET OF INTEL 8085
An Instruction is a command given to the computer to
perform a specified operation on given data. The instruction set of a
microprocessor is the collection of the instructions that the microprocessor is
designed to execute. The instructions described here are of Intel 8085. These
instructions are of Intel Corporation. They cannot be used by other
microprocessor manufactures. The programmer can write a program in assembly
language using these instructions. These instructions have been classified into
the following groups:
1.
Data Transfer Group
2.
Arithmetic Group
3.
Logical Group
4.
Branch Control Group
5.
I/O and Machine Control
Group
Data Transfer Group:
Instructions, which are used to transfer data from one register to another
register, from memory to register or register to memory, come under this group.
Examples are: MOV, MVI, LXI, LDA, STA etc. When an instruction of data transfer
group is executed, data is transferred from the source to the destination
without altering the contents of the source. For example, when MOV A, B is
executed the content of the register B is copied into the register A, and the
content of register B remains unaltered. Similarly, when LDA 2500 is executed
the content of the memory location 2500 is loaded into the accumulator. But the
content of the memory location 2500 remains unaltered.
Arithmetic Group:
The
instructions of this group perform arithmetic operations such as addition,
subtraction; increment or decrement of the content of a register or memory.
Examples are: ADD, SUB, INR, DAD etc.
Logical Group:
The
Instructions under this group perform logical operation such as AND, OR,
compare, rotate etc. Examples are: ANA, XRA, ORA, CMP, and RAL etc.
Branch Control Group:
This group
includes the instructions for conditional and unconditional jump, subroutine
call and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RST etc.
I/O and Machine Control Group:
This group includes the instructions for input/output
ports, stack and machine control. Examples are: IN, OUT, PUSH, POP, and HLT
etc.
1.
Data Transfer Group
a. MOV r1, r2
(Move
Data; Move the content of the one register to another).
[r1]
ß [r2].
b. MOV r, m
(Move the content of memory register). r ß [M]
c. MOV M,
r. (Move the content of register to memory). M ß [r]
d. MVI r,
data. (Move immediate data to register). [r] ß data.
e. MVI M,
data. (Move immediate data to memory). M ß data.
f. LXI rp,
data 16. (Load register pair immediate). [rp] ß data 16
bits, [rh] ß 8 LSBs of data.
g. LDA
addr. (Load Accumulator direct). [A] ß [addr].
h. STA
addr. (Store accumulator direct). [addr] ß [A].
i.LHLD
addr. (Load H-L pair direct). [L] ß [addr], [H] ß [addr+1].
j. SHLD
addr. (Store H-L pair direct) [addr] ß [L], [addr+1] ß [H].
k. LDAX rp.
(LOAD accumulator indirect) [A] ß [[rp]]
l. STAX rp.
(Store accumulator indirect) [[rp]] ß [A].
m. XCHG.
(Exchange the contents of H-L with D-E pair) [H-L] <-->
[D-E].
2.
Arithmetic Group
i.
ADD r. (Add register to
accumulator) [A] ß [A] + [r].
ii.
ADD M. (Add memory to
accumulator) [A] ß [A] + [[H-L]].
iii.
ADC r. (Add register with
carry to accumulator). [A] ß [A] + [r] + [CS].
iv.
ADC M. (Add memory with
carry to accumulator) [A] ß [A] + [[H-L]] [CS].
v.
ADI data (Add immediate
data to accumulator) [A] ß [A] + data.
vi.
ACI data (Add with carry
immediate data to accumulator). [A] ß [A] + data + [CS].
vii.
DAD rp. (Add register paid
to H-L pair). [H-L] ß [H-L] + [rp].
viii.
SUB r. (Subtract register
from accumulator). [A] ß [A] – [r].
ix.
SUB M. (Subtract memory
from accumulator). [A] ß [A] – [[H-L]].
x.
SBB r. (Subtract register
from accumulator with borrow). [A] ß [A] – [r] – [CS].
xi.
SBB M. (Subtract memory
from accumulator with borrow). [A] ß [A] – [[H-L]] – [CS].
xii.
SUI data. (Subtract
immediate data from accumulator) [A] ß [A] – data.
xiii.
SBI data. (Subtract
immediate data from accumulator with borrow).
[A] ß [A] – data – [CS].
xiv. INR r (Increment register
content) [r] ß [r] +1.
xv. INR M. (Increment memory content)
[[H-L]] ß [[H-L]] + 1.
xvi.
DCR r. (Decrement register
content). [r] ß [r] – 1.
xvii.
DCR M. (Decrement memory
content) [[H-L]] ß [[H-L]] – 1.
xviii.
INX rp. (Increment
register pair) [rp] ß [rp] – 1.
xix.
DCX rp (Decrement register
pair) [rp] ß [rp] -1.
xx.
DAA (Decimal adjust
accumulator) .
The instruction DAA is used in the program after ADD,
ADI, ACI, ADC, etc instructions. After the execution of ADD, ADC, etc
instructions the result is in hexadecimal and it is placed in the accumulator.
The DAA instruction operates on this result and gives the final result in the
decimal system. It uses carry and auxiliary carry for decimal adjustment. 6 is
added to 4 LSBs of the content of the accumulator if their value lies in
between A and F or the AC flag is set to 1. Similarly, 6 is also added to 4
MSBs of the content of the accumulator if their value lies in between A and F
or the CS flag is set to 1. All status flags are affected. When DAA is used
data should be in decimal numbers.
3.
Logical Group
i.
ANA r. (AND register with
accumulator) [A] ß [A] ^ [r].
ii.
ANA M. (AND memory with
accumulator). [A] ß [A] ^ [[H-L]].
iii.
ANI data. (AND immediate
data with accumulator) [A] ß [A] ^ data.
iv.
ORA r. (OR register with
accumulator) [A] ß [A] v [r].
v.
ORA M. (OR memory with
accumulator) [A] ß [A] v [[H-L]]
vi.
ORI data. (OR immediate
data with accumulator) [A] ß [A] v data.
vii.
XRA r. (EXCLUSIVE – OR
register with accumulator) [A] ß [A] v [r]
viii.
XRA M. (EXCLUSIVE-OR
memory with accumulator) [A] ß [A] v [[H-L]]
ix.
XRI data. (EXCLUSIVE-OR
immediate data with accumulator) [A] ß 
[A] v data.
x. CMA. (Complement the accumulator) [A]
ß [A]
x.
CMC. (Complement the carry
status) [CS] ß [CS]
xi.
STC. (Set carry status)
[CS] ß 1.
xii.
CMP r. (Compare register
with accumulator) [A] – [r]
xiii.
CMP M. (Compare memory
with accumulator) [A] – [[H-L]]
xiv.
CPI data. (Compare
immediate data with accumulator) [A] – data.
The 2nd byte of the instruction is data,
and it is subtracted from the content of the accumulator. The status flags are
set according to the result of subtraction. But the result is discarded. The
content of the accumulator remains unchanged.
xv.
RLC (Rotate accumulator
left) [An+1] ß [An], [A0] ß [A7],
[CS]
ß [A7].
The
content of the accumulator is rotated left by one bit. The seventh bit of the
accumulator is moved to carry bit as well as to the zero bit of the
accumulator. Only CS flag is affected.
|
A7
|
|
|
|
|
|
|
  A0
|
Carry Status Accumulator
Schematic diagram for RLC
xvi.
RRC. (Rotate accumulator
right) [A7] ß [A0], [CS] ß [A0], [An] ß [An+1].
The content of the accumulator is rotated right by one
bit. The zero bit of the accumulator is moved to the seventh bit as well as to
carry bit. Only CS flag is affected.
|
A7
|
|
|
|
|
|
|
 A0
|
Carry Status
Accumulator
Schematic
Diagram for RRC
xvii.
RAL. (Rotate accumulator
left through carry) [An+1] ß [An], [CS] ß [A7], [A0] ß [CS].
xviii.
RAR. (Rotate accumulator
right through carry) [An] ß [An+1], [CS] ß [A0], [A7] ß [CS]
4.
Branch Group
i.
JMP addr (label).
(Unconditional jump: jump to the instruction specified by the address). [PC] ß Label.
ii.
Conditional Jump addr
(label): After the execution of the conditional jump instruction the program
jumps to the instruction specified by the address (label) if the specified
condition is fulfilled. The program proceeds further in the normal sequence if
the specified condition is not fulfilled. If the condition is true and program
jumps to the specified label, the execution of a conditional jump takes 3
machine cycles: 10 states. If condition is not true, only 2 machine cycles; 7
states are required for the execution of the instruction.
a.
JZ addr (label). (Jump if
the result is zero)
b.
JNZ addr (label) (Jump if
the result is not zero)
c.
JC addr (label). (Jump if
there is a carry)
d.
JNC addr (label). (Jump if
there is no carry)
e.
JP addr (label). (Jump if
the result is plus)
f.
JM addr (label). (Jump if
the result is minus)
g.
JPE addr (label) (Jump if
even parity)
h.
JPO addr (label) (Jump if
odd parity)
iii.
CALL addr (label)
(Unconditional CALL: call the subroutine identified by the operand)
CALL instruction is used to call a subroutine. Before
the control is transferred to the subroutine, the address of the next
instruction of the main program is saved in the stack. The content of the stack
pointer is decremented by two to indicate the new stack top. Then the program
jumps to subroutine starting at address specified by the label.
iv.
RET (Return from
subroutine)
v.
RST n (Restart) Restart is
a one-word CALL instruction. The content of the program counter is saved in the
stack. The program jumps to the instruction starting at restart location.
5. Stack, I/O and Machine Control Group
i.
IN port-address. (Input to
accumulator from I/O port) [A] ß [Port]
ii.
OUT port-address (Output
from accumulator to I/O port) [Port] ß [A]
iii.
PUSH rp (Push the content
of register pair to stack)
iv.
PUSH PSW (PUSH Processor
Status Word)
v.
POP rp (Pop the content of
register pair, which was saved, from the stack)
vi.
POP PSW (Pop Processor
Status Word)
vii.
HLT (Halt)
viii.
XTHL (Exchange stack-top
with H-L)
ix.
SPHL (Move the contents of
H-L pair to stack pointer)
x.
EI (Enable Interrupts)
xi.
DI (Disable Interrupts)
xii.
SIM (Set Interrupt Masks)
xiii.
RIM (Read Interrupt Masks)
xiv.
NOP (No Operation)
ADDRESSING MODES
Each
instruction requires certain data on which it has to operate. There are various
techniques to specify data for instructions.
These techniques are called addressing modes. Intel 8085 uses the following addressing
modes:
i.
Direct addressing
ii.
Register addressing
iii.
Register indirect
addressing
iv.
Immediate addressing
Immediate Addressing
In immediate
addressing mode the operand is specified within the instruction itself,
examples are:
i. MVI
A,05 { Move 05 in register A }
ii. ADI
06 { Add 06 to the content of
the accumulator }
Inter-segment
Direct 
Inter-segment
Modes for
control 
