Digital System Design Through VHDL
Course Code :19A04603
1
Introduction and Field-Programmable Gate Ar-
rays
1. What is a FPGA?
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are
based around a matrix of conÑgurable logic blocks (CLBs) connected via pro-
grammable interconnects. FPGAs can be reprogrammed to desired application
or functionality requirements after manufacturing.
2. What are the characteristics of FPGA?
Lower complexity, higher speed, volume designs and programmable functions are
general characteristics.
1) using FPGA to design ASIC circuit, users can get a suitable chip without chip
production;
2) FPGA can be used as the middle sample chip of other full custom or semi custom
ASIC circuits;
3) There are abundant Òip Òops and I / O pins in FPGA;
4) FPGA is used to design ASIC circuit, which has the advantages of short cycle,
low cost, low risk and stable quality;
5) FPGA adopts high-speed CHMOS technology with low power consumption; 6)
FPGA architecture, Òexible logic unit, high integration and wide application range;
7) FPGA is compatible with the advantages of PLD and general gate array, and
can realize large-scale circuit.
3. What is programmable logic array?
Programmable Logic Array(PLA) is a Ñxed architecture logic device with pro-
grammable AND gates followed by programmable OR gates.
PLA is basically a type of programmable logic device used to build a re conÑgurable
digital circuit.
Applications:
PLA is used to provide control over datapath.
PLA is used as a counter.
PLA is used as a decoder.
1
PLA is used as a BUS interface in programmed I/O.
4. Describe the steps in ASIC design Òow?
Ò Chip SpeciÑcation
Ò Design Entry / Functional VeriÑcation
Ò RTL block synthesis / RTL Function
Ò Chip Partitioning
Ò Design for Test (DFT) Insertion
Ò Floor Planning
Ò Placement
Ò Clock tree synthesis
Ò Routing
Ò Final VeriÑcation (Physical VeriÑcation and Timing)
Ò GDS II Graphical Data Stream Information Interchange
5. What are the diÐerent levels of design abstraction at physical design.
Design application of VHDL to FPGA/ASIC design follows three steps
Algorithm, register transfer level (RTL), and gate level. Algorithms are unsynthe-
sizable, RTL is the input to synthesis, gate level is the output from synthesis
6. What are Programmable Interconnects ?
It provides the routing path for the programmable logic blocks. Routing paths
contain wire segments of varying lengths which can be interconnected via electrically
programmable switches.
7. What are the languages that are combined together to get VHDL lan-
guage ? It is a complex and sophisticated language.
The VHDL language can be regarded as an integrated amalgamation of the follow-
ing languages: sequential language +
concurrent language +
net-list language +
timing speciÑcations +
waveform generation language =>VHDL
2
8. What are sequential and concurrent statements? Sequential Statement:
Whenever one of the signals in the sensitivity list changes, the sequential statements
are executed in sequence once.
Wait Statement Concurrent Statement: signal assignment statements inside ar-
chitecture bodies that are not contained in processes (or body) are called concurrent
statement
Simple Assignment statement
with select statement
9. List out Applications of FPGA
Aerospace, automotive, broadcast, consumer electronics, defense, high-performance
computing, industrial applications, medical applications, and wireless and wired
communications.
10. What are advantages of FGPA It is more feasible than discrete design in wiring
connection. It requires very less space compare to discrete design model. It is
Òexible design compared to discrete digital design.
It requires very less design time compared to ASIC design. It is more programming
Òexible than micro control design.
It consumes very less power compared to microcontroller based design.
11. State the features of VHDL.
Ò Sequential and concurrent activities.
Ò Design exchange.
Ò Standardization.
Ò Documentation.
Ò Readability.
Ò Large-scale design.
Ò A wide range of descriptive capability
12. Name the abstraction levels.
Ò Behavioral or system level
Ò Register Transfer Level (RTL)
Ò Gate Level
Ò Layout level or transistor level
3
13. What does hierarchy mean about? Hierarchy means that design has been
divided in to top level model into lower level model. The top level design has been
viewed as the system level, then it is subdivided into more sub system and then
splitted into lower level of design entities.
14. What are the VHDL structural elements?
Main units in VHDL:
Entity
Architecture
ConÑguration
Package
15. What is entity in VHDL ? A hardware abstraction of this digital system is
called an entity
An ENTITY is a list with specications of all input and output pins (PORTS) of
the circuit.
Syntax :
ENTITY entity name IS
PORT (
port name : signal mode signal type;
port name : signal mode signal type;
...);
END entity name;
16. Write a program for nand gate using dataÒow modeling
library ieee;
use ieee.std logic 1164.all;
entity Nand gate is
port( a, b: in std logic;
c: out std logic);
end Nand gate;
architecture data Òow of Nand gate is
begin
c<= a nand b;
end data Òow;
4
17. Write a progarm of nor gate using Behavioral modeling
library ieee;
use ieee.std logic 1164.all;
entity Nor gate is
port( a, b: in std logic;
c: out std logic);
end Nor gate;
architecture data Òow of Nor gate is
begin
process( a, b)
begin
if( a='1' and b='1') then
c<= '0';
else
c<='1'
end if;
end data Òow;
18. Illustrate the Architecture in VHDL.NOV/DEC-2018
The architecture describes the underlying functionality of the entity and contains
the statements that model the behavior of the entity. An architecture is always
related to an entity and describes the behavior of that entity
The ARCHITECTURE is a description of how the circuit should behave (function).
Syntax - Architecture Dclaration
ARCHITECTURE architecture name OF entity name IS
d- eScilganraaltiDoencslaration, Component declaration etc;
BEGIN
(code)
END architecture name;
An architecture has two parts: a declarative part (optional), where signals and
5
constants (among others) are declared, and the code part (from BEGIN down).
19. What is the application of VHDL?
It is utilized in electronic design automation to express mixed-signal and digital
systems, such as ICs (integrated circuits) and FPGA (Ñeld-programmable gate ar-
rays). We can also use VHDL as a general-purpose parallel programming language.
We utilize VHDL to write text models that describe or express logic circuits.
20. Illustrate the VHDL program Ñle structure. JUNE-2018
Objects of Ñle types represent Ñles in the host environment. They provide a mech-
anism by which a VHDL design communicates with the host environment.
The syntax of a Ñle type declaration is
type Ñle-type-name is Ñle of type-name,
The type-name is the type of values contained in the Ñle. Here are two examples.
type VECTORS is Ñle of BIT VECTOR;
type NAMES is Ñle of STRING;
21. What is structural design element?
The VHDL structural style describes the interconnection of components within an
architecture. structural design uses two parts, namely component declaration and
component instantiations.
Declare the components in the declarative part of the architecture
Instance the component in the architecture statement section
22. What is the diÐerence between signal and variable?
Signals
Ò Signal is an object that keeps it past history
Ò signals are intended to inter process communications
Ò signal assignment schedules a new value for the signal in the future
Ò signals are intended to communicate process and subprograms
Ò Value of the signal must be constant during the entire simulation time
Variable
Ò Variable is an object holds only current value.
Ò variables are intended keeping intermediate computation steps or results
Ò A variable assignment immediately replaces the value of the variable
Ò Variables are used with in the process or subprogram
6
Ò value of the variable must be updated immediately.
23. Write the DiÐerent Data types of HDLs.
ClassiÑcations of Data Type
(a) PredeÑned Data Type
(b) User DeÑned Data Type
PredeÑned Data Type
(a) BIT : It contains the Binary values 0 and 1. E.g SIGNAL x: BIT;
x<='1';
(b) BIT VECTOR:It contains the set of binary values 0 and 1;
(c) STD LOGIC - A 8-valued logic system introduced in the IEEE 1164 stan-
dard.It is the subtype of std ulogic model.
(d) STD LOGIC VECTOR): It is vector format of std logic data
(e) STD ULOGIC (STD ULOGIC VECTOR): 9-level logic system
(f) BOOLEAN: True, False;
(g) INTEGER: 32-bit integers (from 2,147,483,647 to 2,147,483,647).
(h) NATURAL: Non-negative integers (from 0 to +2,147,483,647).
(i) REAL: Real numbers ranging from -1.0E38 to +1.0E38. Not synthesizable.
(j) Physical literals: Used to inform physical quantities, like time, voltage, etc.
(k) Character literals: Single ASCII character or a string of such characters. Not
ynthesizable.
(l) SIGNED and UNSIGNED: data types dened in the std logic arith package
24. Write the Entity declaration. Syntax :
ENTITY entity name IS
PORT (
port name : signal mode signal type;
port name : signal mode signal type;
...);
END entity name;
The mode of the signal can be IN, OUT, INOUT, or BUFFER
IN and OUT are truly unidirectional pins, while INOUT is bidirectional.BUFFER
is used when the output signal must be read internally The type of the signal can
7
be BIT, STD LOGIC, INTEGER, etc
The name of the entity can be basically any name, except VHDL reserved words
Example - Entity Declartion for nand gate
ENTITY nand gate IS
PORT (a, b : IN BIT;
x:OUT BIT);
END nand gate;
8
